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ISL26132, ISL26134
18
FN6954.1
September 9, 2011
Operation of PDWN
PDWN must transition from low to high after both power supplies
have settled to specified levels in order to initiate a correct
power-up reset (Figure 35). This can be implemented by an
external controller or a simple RC delay circuit, as shown in
Figure 36.
In order to reduce power consumption, the user can assert the
Power-down mode by bringing PDWN Low as shown in Figure 37.
All circuitry is shut down in this mode, including the Crystal
Oscillator. After PDWN is brought High to resume operation, the
reset delay varies depending on the clock source used. While an
external clock source will resume operation immediately, a
circuit utilizing a crystal will incur about a 20 millisecond delay
due to the inherent start-up time of this type of oscillator.
FIGURE 35. POWER-DOWN TIMING RELATIVE TO SUPPLIES
≥10s
AVDD
DVDD
PDWN
FIGURE 36. PDWNDELAY CIRCUIT
DVDD
1k
Ω
2.2nF
CONNECT TO
PDWN PIN
FIGURE 37. POWER-DOWN MODE WAVEFORMS
SDO/RDY
SCLK
t11
PDWN
POWER-DOWN
MODE
START
CONVERSION
DATA
READY
CLK
SOURCE
WAKEUP
t13
t14
t14
TABLE 14. POWER-DOWN RECOVERY TIMING
PARAMETER
DESCRIPTION
TYP
UNITS
t13
Clock Recovery after PDWN
High
Internal Oscillator
7.95
s
External Clock Source
0.16
s
4.9152MHz Crystal
Oscillator
5.6
ms
t14
PDWN Pulse Duration
26
s (min)
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